Sparse Convolution FPGA Accelerator Based on Multi-Bank Hash Selection - Xu, Jia; Pu, Han; Wang, Dong (Micromachines (Basel), 2024)
Keywords: Accelerators; Algorithms; Artificial intelligence; Artificial neural networks; Bandwidths; cache memory; Chips (memory devices); Computing time; deep convolutional neural network; Design; Energy efficiency; Feature maps; Field programmable gate arrays; FPGA; heterogeneous computing; high-level synthesis; Inference; Microprocessors; Network latency; Neural networks; Optimization; Power consumption; Power management; Redundancy; cache memory; heterogeneous computing; high-level synthesis; deep convolutional neural network; FPGA