Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 11; no. 2; pp. 208 - 217
• Main Authors: Kittitornkun, S., Yu Hen Hu
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.04.2003; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Applied sciences; Circuit properties; Design automation; Design engineering; Design methodology; Design. Technologies. Operation analysis. Testing; Digital circuits; Digital signal processing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Field programmable gate arrays; Graphs; Integrated circuits; Integrated circuits by function (including memories and processors); Large-scale systems; Linear arrays; Logic devices; Logic gates; Logic programming; Mapping; Methodology; Programmable logic arrays; Reconfigurable logic; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; Very large scale integration; Performance evaluation; Array processor; Circuit design; field programmable gate arrays (FPGAs); Linear array; Logic gate; high-level synthesis; Mapping; Field programmable gate array; Systolic network; Algorithm; Implementation; Periodic structure; Look up table; Logic circuit; Integrated circuit; systolic array; Parallelism; Reconfigurable architectures; Large scale; Digital signal processor; parallel computing; Computer aided design; Dependence graph
• ISSN: 1063-8210; 1557-9999; 1557-9999
• DOI: 10.1109/TVLSI.2002.801622

Recently, FPGAs (field programmable gate arrays) technology have made significant advances in both speed and capacity. Millions of logic gates are now available for reconfiguration programming. To fully exploit the potential of so many programmable devices, powerful design methodology must be developed. In this paper, we propose a novel systematic computer-aided design methodology that can efficiently implement deeply nested do-loop algorithms on a FPGA. Specifically, our design methodology maps the loop dependence graph onto a linear array of locally connected processing elements to exploit parallelism. Due to the regular structure of this linear array of processors, it can be easily implemented on a FPGA. While this method is based on conventional systolic array design methodology, our proposed approach exhibits two distinct features that contribute to its superior performance: 1) We developed a novel multiple-order dependence graph representation that is able to efficiently represent distinct, yet correct algorithm execution orders. 2) We developed new FPGA-specific architectural constraints during the mapping process. As such, FPGA implementations based on our approach will utilize much fewer lookup tables while achieving superior performance.