A high efficiency charge pump circuit for low power applications

• Published in: Journal of semiconductors Vol. 31; no. 1; pp. 88 - 92
• Main Author: 冯鹏 李昀龙 吴南健
• Format: Journal Article
• Language: English
• Published: IOP Publishing 2010
• Subjects: CMOS工艺; 低功耗; 应用; 收费; 晶体管开关; 电荷泵电路; 阈值电压; 高效率
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/31/1/015009

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.