Statistical Path Selection for At-Speed Test

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 29; no. 5; pp. 749 - 759
• Main Authors: Zolotov, Vladimir, Jinjun Xiong, Fatemi, Hanif, Visweswariah, Chandu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Application specific integrated circuits; At-speed test; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Computer aided design; Delay; Design engineering; Fault detection; Fault diagnosis; Faults; Gates; Propagation delay; Space technology; statistical path selection; statistical timinng; testing; Time measurements; Timing; Unions
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2010.2043570

Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed in contrast to the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process space, and the union of such paths must be tested to obtain good process space coverage. This paper proposes an integrated at-speed structural testing methodology, and develops a novel branch-and-bound algorithm that elegantly and efficiently solves the hitherto open problem of statistical path tracing. The resulting paths are used for at-speed structural testing. A new test quality metric is proposed, and paths which maximize this metric are selected. After chip timing has been performed, the path selection procedure is extremely efficient. Path selection for a multimillion gate chip design can be completed in a matter of seconds.