PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

• Published in: Measurement and control (London) Vol. 55; no. 1-2; pp. 3 - 12
• Main Authors: Heo, Hyunwoo, Kim, Hyungseup, You, Donggeun, Kwon, Yongsu, Yang, Yil-suk, Lee, Junghoon, Ko, Hyoungho
• Format: Journal Article
• Language: English
• Published: London, England SAGE Publications 01.01.2022; Sage Publications Ltd; SAGE Publishing
• Subjects: Algorithms; Automatic control; Automatic gain control; Cancellation; Capacitance; CMOS; Equivalent circuits; Frequency response; Inductance; Integrated circuits; Metal oxides; Motional resistance; Parasitics (electronics); Phase distortion; Phase locked loops; Phase noise; Q factors; Resonant frequencies; Resonators; Trouble shooting; Voltage controlled oscillators; automatic parasitic capacitance cancellation; motional series resonant frequency; Phase-locked loop; automatic gain control; Butterworth-Van Dyke equivalent circuit model
• ISSN: 0020-2940; 2051-8730; 2051-8730
• DOI: 10.1177/00202940211029335

This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth–Van Dyke equivalent circuit model with motional resistance of 72.8 kΩ, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm2. The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the quality factor (Q-factor) is 59,590.