High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

• Published in: IEEE transactions on electron devices Vol. 60; no. 1; pp. 360 - 365
• Main Authors: Shimamoto, S., Yanagida, Y., Shirakawa, S., Miyakoshi, K., Oshima, T., Sakano, J., Wada, S., Noguchi, J.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.2013; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Channels; Compound structure devices; Drains; Electric potential; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Harmonic analysis; High-voltage (HV) techniques; Imaging; Ion implantation; Layout; Metals; MOSFETs; Optimization; Other multijunction devices. Power transistors. Thyristors; Platforms; power MOSFETs; power semiconductor devices; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; silicon-on-insulator (SOI) technology; Transistors; Voltage; Surface field; High-voltage (HV) techniques; High strength current; High performance; MOSFET; Lateral diffusion; Channel structure; MOS structure; n channel; Power electronics; silicon-on-insulator (SOI) technology; Surface structure; Power transistor; Silicon on insulator technology; p channel; Disruptive voltage; power MOSFETs; High-voltage techniques; Drain current; Power device; power semiconductor devices; MOS transistor; Double diffusion; On off effect
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2012.2228202

High-performance p-channel lateral double-diffused MOS (LDMOS) transistors designed to operate in a wide voltage range from 35 to 200 V and built using silicon-on-insulator LDMOS platform technology were studied. A novel channel structure was applied, and consequently, a high saturation drain current of 172 μA/μm in the 200-V p-channel LDMOS transistor was achieved, which is comparable to that of an n-channel LDMOS transistor. A low on -resistance of 3470 mΩ·mm 2 was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35-200-V LDMOS transistors with low on-resistance were also demonstrated by optimizing the layout, i.e., the reduced surface field structure and field plates.