A SiGe BiCMOS Amplifier-Frequency Doubler Chain Operating for 284–328 GHz

This work describes the development of an amplifier frequency doubler chain (AFDC) operating at around 300 GHz based on SiGe BiCMOS technology. The driver amplifier is based on the differential cascode configuration, which employs coupled-line transformers for compact design. The frequency doubler i...

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Bibliographic Details
Published inJournal of Electromagnetic Engineering and Science Vol. 22; no. 2; pp. 114 - 121
Main Authors Yoo, Junghwan, Kim, Jungsoo, Yun, Jongwon, Kaynak, Mehmet, Rieh, Jae-Sung
Format Journal Article
LanguageEnglish
Published 한국전자파학회JEES 01.03.2022
The Korean Institute of Electromagnetic Engineering and Science
한국전자파학회
Subjects
amplifier
frequency doubler
heterojunction bipolar transistor (hbt)
silicon germanium
전자/정보통신공학
Amplifier
Frequency Doubler
Heterojunction Bipolar Transistor (HBT)
Silicon Germanium
Online AccessGet full text
ISSN2671-7255
2671-7263
DOI10.26866/jees.2022.2.r.67

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Summary:This work describes the development of an amplifier frequency doubler chain (AFDC) operating at around 300 GHz based on SiGe BiCMOS technology. The driver amplifier is based on the differential cascode configuration, which employs coupled-line transformers for compact design. The frequency doubler is based on the class-B topology, which is known for exhibiting a large output power with low DC power consumption. The integrated AFDC, which consists of the frequency doubler and the preceding driver amplifier, exhibited a measured peak output power and DC-to-RF efficiency of -0.9 dBm and 0.97%, respectively, along with a conversion gain of -0.1 dB. It operates from 284 to 328 GHz with a 0-dBm input signal, consuming a total DC power of only 84 mW. The chip size is 720 × 310 μm2, excluding RF and DC pads.
ISSN:2671-7255
2671-7263
DOI:10.26866/jees.2022.2.r.67