CCNoC： Cache-Coherent Network on Chip for Chip Multiprocessors

• Published in: Journal of computer science and technology Vol. 25; no. 2; pp. 257 - 266
• Main Author: 王惊雷 薛一波 Member, CCF, IEEE 王海霞 李崇民 汪东升 Senior Member,CCF
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.03.2010; Springer Nature B.V; Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China%Tsinghua National Laboratory of Information Science and Technology, Beijing 100084, China%Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China; Tsinghua National Laboratory of Information Science and Technology, Beijing 100084, China
• Subjects: Artificial Intelligence; Chemical-mechanical polishing; Chips; Chips (electronics); Coherence; Complexity; Computer Science; Data Structures and Information Theory; Directories; Directory; Information management; Information Systems Applications (incl.Internet); Multiprocessing; Multiprocessor; Networks; Performance enhancement; Performance evaluation; Processors; Protocol; Protocol (computers); Regular Paper; Software Engineering; System on chip; Theory of Computation; 一致性协议; 一致性维护; 二级高速缓存; 多处理器芯片; 片上网络; 目录信息; network on chip; chip multiprocessor; cache coherence protocol
• ISSN: 1000-9000; 1860-4749
• DOI: 10.1007/s11390-010-9322-4

As the number of cores in chip multiprocessors （CMPs） increases, cache coherence protocol has become a key issue in integration of chip multiprocessors. Supporting cache coherence protocol in large chip multiprocessors still faces three hurdles： design complexity, performance and scalability. This paper proposes Cache Coherent Network on Chip （CCNoC）, a scheme that decouples cache coherency maintenance from processors and shared L2 caches and implements it completely in network on chip to free up processors and shared L2 caches from the chore of maintaining coherency, thereby reduces design complexity of CMPs. In this way, CCNoC also improves the performance of cache coherence protocol through reducing directory access latency and enhances scalability by avoiding massive directories overhead in shared L2 caches. In CCNoC, coherence state caches and active directory caches are implemented in the network interface components of network on chip to maintain cache coherence states for blocks in L1 caches and manage directory information for recently accessed blocks in L2 caches respectively. CCNoC provides a scalable CMP framework to tackle cache coherency which is the foundation of CMP. This paper evaluates the performance of CCNoC. Experimental results show that for a 16-core system, CCNoC improves performance by 3% on average over the conventional chip multiprocessor and by 10% at best, while reduces storage overhead by 1.8% and saves directory storage by 88%, showing good scalability.