High-Resolution Waveform Capture Device on a Cyclone-V FPGA

• Published in: IEEE access Vol. 9; pp. 146203 - 146213
• Main Authors: Charlot, Noeloikeau F., Gauthier, Daniel J., Pomerance, Andrew
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Calibration; carry chain (CC); Clocks; Converters; Cyclones; digital storage oscilloscope (DSO); dynamic phase shift (DPS); Error correction; field programmable gate array (FPGA); Field programmable gate arrays; Oscillators; Oscilloscopes; phase lock loop (PLL); Phase locked loops; Power transmission lines; Pulse duration; Registers; Time-to-digital converter (TDC); Transmission line measurements; Transmission lines; Waveforms
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2021.3123277

We introduce the waveform capture device (WCD), a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD is implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA, Intel/Altera Cyclone V), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It is calibrated via a novel dynamic phase-shifting (DPS) method that requires substantially less data and resources than the state-of-the-art. Using DPS, we find the measurement resolution - or mean propagation delay from one CC element to the next - to be 4.91±0.04 ps (4.54±0.02 ps) for a pulse of logic high (low). Similarly, we find the single-shot precision - or mean error on the timing of the waveform - to be 29.52 ps (27.14 ps) for pulses of logic high (low). We verify these findings by reproducing commercial oscilloscope measurements of asynchronous ring-oscillators on FPGAs, finding the mean pulse width to be 0.240 ± 0.002 ns per inverter gate. Finally, we present a careful analysis of design constraints, introduce a novel error correction algorithm, and sketch a simple extension to the analog domain. We also provide the Verilog code instantiating our design's hardware primitives in an Appendix, and make our FPGA interfacing methods available as an open-source Python library at https://github.com/Noeloikeau/fpyga .