Reconfigurable Scan Architecture for High Diagnostic Resolution

• Published in: IEEE access Vol. 9; pp. 120537 - 120550
• Main Authors: Jang, Seokjun, Kim, Jihye, Kang, Sungho
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Chains; Circuit faults; Circuits; Computer architecture; Cost analysis; Design for testability; Diagnostic systems; Failure analysis; Fault diagnosis; flush test; Hardware; hardware-based scan chain diagnosis; Miniaturization; multiple faults; Multiplexing; Ports (computers); Reconfiguration; Routing; Transistors
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2021.3108429

Scan chain diagnosis is essential to solving yield-reduction problem caused by the miniaturization of manufacturing process. The accurate diagnosis of scan chain faults that frequently occur in the initial process is vital for rapidly improving yield. Moreover, the importance of scan chain diagnosis with a high resolution for the multiple faults is increasing because multiple faults occur in the early stages of the process, further increasing the cost of physical failure analysis. Although multiple faults can be diagnosed with existing methods, a high diagnostic resolution is difficult to achieve in the early stages of the process (where many faults occur) due to the rapid increase in the number of diagnosed fault candidates as the number of actual faults in the circuit increases. In this paper, a novel reconfigurable scan architecture that reconfigures the diagnosis paths and a test algorithm that uses this scan architecture are proposed to reduce the number of diagnosed fault candidates in the scan chain diagnosis with multiple circuit faults. Experimental results indicate that the proposed method achieves the higher diagnostic resolution for multiple faults than conventional methods. In addition, the proposed method reduces the routing overhead by scan partitioning.