Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation - Chung-Ping Chen; Chu, C.C.N.; Wong, D.F. (IEEE transactions on computer-aided design of integrated circuits and systems, 1999)
Keywords: Algorithms; Applied sciences; Circuit optimization; Circuits; Delay; Delay effects; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Gates (circuits); Integrated circuit interconnections; Integrated circuit technology; Integrated circuits; Iterative algorithms; Lagrangian functions; Large-scale systems; Optimization; Routing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sizing; Very large scale integration; Wire; Performance evaluation; Relaxation; VLSI circuit; Circuit design; Interconnection; Optimal solution; Iterative method; Elmore delay; Fast algorithm; Lagrangian method; Optimization