Low power 2D finite impulse response filter design using modified artificial bee colony algorithm with experimental validation using field-programmable gate array

• Published in: IET science, measurement & technology Vol. 10; no. 6; pp. 671 - 678
• Main Authors: Dwivedi, Atul Kumar, Ghosh, Subhojit, Londhe, Narendra D
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 01.09.2016
• Subjects: Algorithms; band‐pass filters; band‐stop filters; circular shaped 2D FIR filter; cooling; Design analysis; Design modifications; field programmable gate arrays; field‐programmable gate array; FIR filters; frequency domain analysis; Hamming distance; Impulse response; low power 2D finite impulse response filter design; low power two‐dimensional FIR filter; maintenance; Mathematical analysis; minimisation; modified artificial bee colony algorithm; optimisation problem; pass band ripple minimisation; power consumption; Ripples; singular value decomposition; stop band ripple minimisation; Two dimensional; Xilinx X‐power analyser; Hamming distance; field programmable gate arrays; circular shaped 2D FIR filter; Xilinx X-power analyser; modified artificial bee colony algorithm; field-programmable gate array; pass band ripple minimisation; power consumption; optimisation problem; frequency domain analysis; FIR filters; low power two-dimensional FIR filter; low power 2D finite impulse response filter design; PC; band-pass filters; cooling; minimisation; maintenance; singular value decomposition; band-stop filters; stop band ripple minimisation
• ISSN: 1751-8822; 1751-8830
• DOI: 10.1049/iet-smt.2016.0069

Motivated by the need of reducing power consumption (PC) in two dimensional (2D) finite impulse response (FIR) filters, in this work, the 2D FIR filter design task is formulated as an optimisation problem that seeks to attain the desired frequency response and reduces PC. The optimisation problem has been solved using the modified version of artificial bee colony algorithm. The applicability of the proposed approach has been evaluated by designing circular shaped 2D FIR filters for a set of specifications in frequency domain. The designed filters have been compared with other reported state of the art techniques. The evaluation is carried out in terms of pass band and stop band ripple minimisation, convergence profile and PC during filter execution in hardware. The proposed technique is found to outperform all other techniques in achieving minimum ripple for a given filter order. To prove the effectiveness of the proposed approach for PC reduction, the designed filters have been implemented in hardware using field-programmable gate array (xc7vx485t-2ffg1761). The PC computed using Xilinx X-power analyser shows that 23.53% power can be saved using the proposed approach as compared with conventional design approaches.