Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations - Denic, S Z; Vasic, B; Charalambous, C D; Jifeng Chen; Wang, J M (IEEE transactions on very large scale integration (VLSI) systems, 2011)
Keywords: Achievable rate; Applied sciences; bit error rate process variations; Buses (vehicles); CMOS process; CMOS technology; Computation; Computational modeling; Computer errors; Computer simulation; Design engineering; Design. Technologies. Operation analysis. Testing; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Electronics industry; Exact sciences and technology; global interconnect; Information analysis; Information theory; Integrated circuits; Manufacturing processes; Mathematical models; Nanoscale devices; Semiconductor device manufacture; Semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Very large scale integration; Virtual manufacturing; Lower bound; global interconnect; Bit error rate; Achievable rate; Bus(channel); Modeling; bit error rate process variations; Coding; Interconnection; Complementary MOS technology; Integrated circuit; Delay time; Data communication; Wafer; Information theory