APA (7th ed.) Citation

Denic, S. Z., Vasic, B., Charalambous, C. D., Chen, J., & Wang, J. M. (2011). Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations. IEEE transactions on very large scale integration (VLSI) systems, 19(3), 397-410. https://doi.org/10.1109/TVLSI.2009.2033933

Chicago Style (17th ed.) Citation

Denic, S Z., B. Vasic, C D. Charalambous, Jifeng Chen, and J M. Wang. "Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 3 (2011): 397-410. https://doi.org/10.1109/TVLSI.2009.2033933.

MLA (9th ed.) Citation

Denic, S Z., et al. "Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 3, 2011, pp. 397-410, https://doi.org/10.1109/TVLSI.2009.2033933.