ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs

• Published in: IEEE transactions on electron devices Vol. 64; no. 3; pp. 930 - 937
• Main Authors: Wang, Jian, Chen, Zhe, Guo, Jinhong, Li, Yubai, Lu, Zhonghai
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Ant colony optimization; Chip multiprocessor (CMP); Constraints; dark silicon; Heuristic algorithms; Instruction sets; Mapping; Multiprocessing; Prediction models; Predictive models; Silicon; Temperature; Thermal management; thermal model; thread-to-core mapping
• ISSN: 0018-9383; 1557-9646; 1557-9646
• DOI: 10.1109/TED.2017.2653838

The limitation on thermal budget in chip multiprocessor (CMP) results in a fraction of inactive silicon regions called dark silicon, which significantly impacts the system performance. In this paper, we propose a thread-to-core mapping method for dark-silicon-constrained CMPs to address their thermal issue. We first propose a thermal prediction model to forecast CMP temperature after the CMP executes a forthcoming application. Then, we develop an ant colony optimization-based algorithm to conduct the thread-to-core mapping process, such that the CMP peak temperature is minimized and, consequently, the probability of triggering CMP dynamic thermal management is decreased. Finally, we evaluate our method and compare it with the baseline (a standard Linux scheduler) and other existing methods (NoC-Sprinting, DaSiM mapping, and TP mapping). The simulation results show that our method gains good thermal profile and computational performance, and performs well with chip scaling. Specifically, it eliminates all thermal emergency time, outperforming all other methods, and gains million instructions per second improvement up to 12.9% against the baseline.