HERMES: an infrastructure for low area overhead packet-switching networks on chip

• Published in: Integration (Amsterdam) Vol. 38; no. 1; pp. 69 - 93
• Main Authors: Moraes, Fernando, Calazans, Ney, Mello, Aline, Möller, Leandro, Ost, Luciano
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.10.2004
• Subjects: Core based design; Network on chip; On-chip interconnection; Switches; System on a chip; On-chip interconnection; System on a chip; Core based design; Network on chip; Switches
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2004.03.003

The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional on-chip bus architectures. This paper reviews the state of the art in networks on chip. Then, it describes an infrastructure called Hermes, targeted to implement packet-switching mesh and related interconnection architectures and topologies. The basic element of Hermes is a switch with five bi-directional ports, connecting to four other switches and to a local IP core. The switch employs an XY routing algorithm, and uses input queuing. The main design objective was to develop a small size switch, enabling its immediate practical use. The paper also presents the design validation of the Hermes switch and of a network on chip based on it. A Hermes NoC case study has been successfully prototyped in hardware as described in the paper, demonstrating the functionality of the approach. Quantitative data for the Hermes infrastructure is advanced.