Continuous time sigma delta ADC design and non-idealities analysis

A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed nonidealities analysis （excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch） is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applicati...

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Published inJournal of semiconductors Vol. 32; no. 12; pp. 128 - 133
Main Author 袁俊 张钊锋 吴俊 王超 陈珍海 钱文荣 杨银堂
Format Journal Article
LanguageEnglish
Published IOP Publishing 01.12.2011
Subjects
Bandwidth
Clocks
Deltas
Design engineering
Matlab
Modulators
Noise levels
Semiconductors
sigma
Simulink
Σ-ΔADC
Σ-Δ调制器
设计
连续时间
非理想
Online AccessGet full text
ISSN1674-4926
DOI10.1088/1674-4926/32/12/125007

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Summary:A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed nonidealities analysis （excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch） is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. A third-order continuous time sigma delta modulator comprises a third-order RC operational- amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.
Bibliography:A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed nonidealities analysis （excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch） is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. A third-order continuous time sigma delta modulator comprises a third-order RC operational- amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.
11-5781/TN
ADC; continuous time; sigma delta ADC; low power design; sigma delta modulation
Yuan Jun, Zhang Zhaofeng, Wu Jun, Wang Chao, Chen Zhenhai, Qian Wenrong, and Yang Yintang（ 1 School of Microelectronics, Xidian University, Xi＇an 710071, China 2Marvell Technology Group, Ltd., Shanghai 201203, China 3 Shanghai Advanced Research Institute, Chinese Academy of Sciences,201203,China）
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ISSN:1674-4926
DOI:10.1088/1674-4926/32/12/125007