The investigation on sensitive mapping of memory cell in microprocessor

• Published in: Journal of semiconductors Vol. 36; no. 11; pp. 44 - 47
• Main Author: 于春青 范隆 岳素格 陈茂鑫 杜守刚 郑宏超
• Format: Journal Article
• Language: English
• Published: Chinese Institute of Electronics 01.11.2015
• Subjects: 32位微处理器; Circuits; Drains; Hardening; Mapping; Memory (computers); memory cells; microprocessor; Microprocessors; Pulsed lasers; Semiconductors; sensitive mapping; single event effects; 单粒子效应; 存储单元; 指令流水线; 敏感性; 映射; 激光测试; 电路布局
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/36/11/114005

The single event effects of the sensitivity of a circuit are investigated on a 32-bit microprocessor with a five-stage instruction pipeline by pulsed laser test. The investigation on sensitive mapping of the memory cell is illustrated and then the comparison between the sensitive mapping and the layout of the circuit is made. A comparison result indicates that the area of the sensitive node in sensitive mapping is just the location of the drain in the layout. Therefore, SEE sensitivity in sensitive mapping fits well with that in the physical layout of functional units, which can directly and objectively indicate the size and distribution of sensitive areas. The investigation of sensitive mapping is a meaningful way to verify the hardened effect and provide a reference for improving hardened design by combining with the physical layout.