Efficient CTDSM based on GM-C quantiser and improved dynamic element matching

• Published in: IET circuits, devices & systems Vol. 14; no. 5; pp. 680 - 685
• Main Authors: Sahu, Anil Kumar, Chandra, Vivek Kumar, Sinha, Ganesh Ram, Kumar Misra, Neeraj
• Format: Journal Article
• Language: English
• Published: Stevenage The Institution of Engineering and Technology 01.08.2020; John Wiley & Sons, Inc
• Subjects: Algorithms; bandwidth 20.0 kHz; Bandwidths; Calibration; CMOS integrated circuits; CMOS technology; continuous-time delta-sigma modulator; CTDSM; delta-sigma modulation; digital-to-analogue converters; dynamic latches; Feedback; frequency 2.6 MHz; Gm-C based noise-shaping quantiser; Gm-C integrator; Gm-C-NSQ; i-DEM algorithm; improved dynamic element matching algorithm; integrated circuit design; Latches; Matching; Modulators; Noise levels; peak signal-to-noise ratio; power 0.0863 mW; quantisation (signal); Research Article; voltage 1.2 V; digital-to-analogue converters; i-DEM algorithm; voltage 1.2 V; continuous-time delta-sigma modulator; dynamic latches; peak signal-to-noise ratio; frequency 2.6 MHz; power 0.0863 mW; delta-sigma modulation; Gm-C-NSQ; Gm-C based noise-shaping quantiser; integrated circuit design; quantisation (signal); Gm-C integrator; CMOS technology; CTDSM; CMOS integrated circuits; bandwidth 20.0 kHz; improved dynamic element matching algorithm
• ISSN: 1751-858X; 1751-8598; 1751-8598
• DOI: 10.1049/iet-cds.2019.0404

In this study, a continuous-time delta-sigma modulator (CTDSM) is developed using a Gm-C based noise-shaping quantiser (Gm-C-NSQ) with an improved dynamic element matching (i-DEM) algorithm. Here, a Gm-C integrator is used to develop NSQ, since it increases the effectiveness of the proposed modulator in terms of power consumption and die area. This Gm-C-NSQ uses only three dynamic latches to provide efficient quantisation level and to increase the order of noise shaping. Moreover, an i-DEM algorithm is utilised to reduce the non-linearities of the quantiser and mismatching error of the digital-to-analogue converters presented in the feedback structure of the modulator. Here, an 180 nm CMOS technology is used to design the proposed modulator and it functions at 2.6 MHz sampling frequency. Simulation results show that the proposed modulator can achieve a peak spurious-free dynamic range (SFDR) of 93.67 dB and a peak signal-to-noise ratio of 87.38 dB for 20 kHz signal bandwidth. Furthermore, the proposed modulator consumes 0.0863 mW power when 1.2 V supply voltage is applied.