Grammatical Evolution of Complex Digital Circuits in SystemVerilog
The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects...
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| Published in | SN computer science Vol. 3; no. 3; p. 188 |
|---|---|
| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
Singapore
Springer Nature Singapore
01.05.2022
Springer Nature B.V |
| Subjects | |
| Online Access | Get full text |
| ISSN | 2662-995X 2661-8907 2661-8907 |
| DOI | 10.1007/s42979-022-01045-9 |
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| Abstract | The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit
×
64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit
×
64-bit and 128-bit
×
128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit
×
N-bit multiplier. The Adder (6.4
×
), Multiplier (10.7
×
) and Selective Parity (6.7
×
) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog. |
|---|---|
| AbstractList | The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit × 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit × 64-bit and 128-bit × 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit × N-bit multiplier. The Adder (6.4×), Multiplier (10.7×) and Selective Parity (6.7×) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog. The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit $$\times$$ × 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit $$\times$$ × 64-bit and 128-bit $$\times$$ × 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit $$\times$$ × N-bit multiplier. The Adder (6.4 $$\times$$ × ), Multiplier (10.7 $$\times$$ × ) and Selective Parity (6.7 $$\times$$ × ) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog. The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit × 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up-Down Counter circuits at a more abstract level other than gate level-register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit × 64-bit and 128-bit × 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit × N-bit multiplier. The Adder (6.4 × ), Multiplier (10.7 × ) and Selective Parity (6.7 × ) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog.The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit × 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up-Down Counter circuits at a more abstract level other than gate level-register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit × 64-bit and 128-bit × 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit × N-bit multiplier. The Adder (6.4 × ), Multiplier (10.7 × ) and Selective Parity (6.7 × ) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog. The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up-Down Counter circuits at a more abstract level other than gate level-register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit 64-bit and 128-bit 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit N-bit multiplier. The Adder (6.4 ), Multiplier (10.7 ) and Selective Parity (6.7 ) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog. The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit $$\times$$ × 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit $$\times$$ × 64-bit and 128-bit $$\times$$ × 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit $$\times$$ × N-bit multiplier. The Adder (6.4 $$\times$$ ×), Multiplier (10.7 $$\times$$ ×) and Selective Parity (6.7 $$\times$$ ×) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog. The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing required and the low evolvability of representation structures to handle complex circuitry, at least partially due to the destructive effects of genetic operators. A 64-bit × 64-bit add-shift multiplier circuit modelled at register-transfer level in SystemVerilog would require approximately 33,200 gates when synthesized using Yosys Open SYnthesis Suite tool. This enormous gate count makes evolving such a circuit at the gate-level difficult. We use Grammatical Evolution (GE) and SystemVerilog, a hardware description language (HDL), to evolve fully functional parameterized Adder, Multiplier, Selective Parity and Up–Down Counter circuits at a more abstract level other than gate level—register transfer level. Parameterized modules have the additional benefit of not requiring a re-run of evolutionary experiments if multiple instances with different input sizes are required. For example, a 64-bit × 64-bit and 128-bit × 128-bit multipliers etc., can be instantiated from a fully evolved functional and parameterized N-bit × N-bit multiplier. The Adder (6.4 × ), Multiplier (10.7 × ) and Selective Parity (6.7 × ) circuits are substantially larger than the current state of the art for evolutionary approaches. We are able to scale so dramatically because of the use of a HDL, which permits us to operate at a register-transfer level. Furthermore, we adopt a well known technique for reducing testing from digital circuit design known as corner case testing. Skilled circuit designers rely on this to avoid time-consuming exhaustive testing. We demonstrate a simple way to identify and use corner cases for evolutionary testing and show that it enables the generation of massively complex circuits. All circuits were successfully evolved without resorting to the use of any standard decomposition methods, due to our ability to use programming constructs and operators available in SystemVerilog. |
| ArticleNumber | 188 |
| Author | Ryan, Conor Tetteh, Michael Dias, Douglas Mota |
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| BackLink | https://www.ncbi.nlm.nih.gov/pubmed/35308804$$D View this record in MEDLINE/PubMed |
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| Keywords | SystemVerilog Grammatical evolution Evolutionary design of conventional circuits Verilog Register transfer level (RTL) Hardware description language (HDL) Combinational circuits Sequential circuits Evolvable hardware Corner case testing |
| Language | English |
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Genetic Programming: 24th European Conference, EuroGP 2021, Held as Part of EvoStar 2021, Virtual Event, April 7–9, 2021, Proceedings, vol. 12691, Springer Nature, 2021, vol. 12691, pp. 66. Fišer P, Schmidt J, Vašíček Z, Sekanina L. 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems 2010;346–351. https://doi.org/10.1109/DDECS.2010.5491755. Vassilev VK, MillerJF. Proc. Genetic and Evolutionary Computation Conference. Morgan Kaufmann, 2000. Sekanina L, Vasicek Z. 2013 IEEE International Conference on Evolvable Systems (ICES). 2013;21–28. https://doi.org/10.1109/ICES.2013.6613278. AliBAlmainiAEAKalganovaTGenet Program Evol Mach2004511110.1023/B:GENP.0000017009.11392.e2 Keymeulen D, Zebulum R, Rajeshuni R, Stoica A, Katkoori S, Graves S, Novak F, Antill C. First NASA/ESA Conference on Adaptive Hardware and Systems (AHS’06) 2006, pp 296–300. https://doi.org/10.1109/AHS.2006.64. Hrbacek R, Sekanina L. Proceedings of the 2014 Annual Conference on Genetic and Evolutionary Computation. Association for Computing Machinery, New York, NY, USA, 2014, GECCO ’14, pp 1015-1022. https://doi.org/10.1145/2576768.2598343. Stuart Sutherland PF, Davidmann S. A Guide to Using SystemVerilog for Hardware Design and Modeling, chap. Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions and Chapter 7: SystemVerilog Procedural Statements, pp. 137–206. in [39]. https://doi.org/10.1007/0-387-36495-1. VasicekZSekaninaLIEEE Trans Evol Comput201519343210.1109/TEVC.2014.2336175 Anjum MS, Ryan C. In: Hu T, Lourenço N, Medvet E (eds) Programming Genetic. Cham: Divina Springer International Publishing; 2020, pp 18–34. BJ LaMeres (1045_CR19) 2019 1045_CR20 1045_CR21 1045_CR22 1045_CR23 1045_CR24 1045_CR25 1045_CR26 1045_CR28 1045_CR29 1045_CR50 1045_CR51 1045_CR52 1045_CR10 Z Vasicek (1045_CR43) 2015; 19 1045_CR11 1045_CR12 1045_CR14 1045_CR15 1045_CR16 JF Miller (1045_CR27) 2011 1045_CR17 1045_CR18 1045_CR40 1045_CR41 1045_CR44 1045_CR45 1045_CR5 1045_CR46 1045_CR4 1045_CR47 1045_CR3 1045_CR48 1045_CR2 1045_CR49 1045_CR1 1045_CR9 1045_CR8 B Ali (1045_CR13) 2004; 5 1045_CR7 1045_CR6 1045_CR30 1045_CR31 1045_CR32 1045_CR33 1045_CR34 1045_CR35 1045_CR36 1045_CR37 1045_CR38 1045_CR39 K Senthilkumar (1045_CR42) 2020; 16 |
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| Snippet | The evolution of complex circuits remains a challenge for the Evolvable Hardware field in spite much effort. There are two major issues: the amount of testing... |
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| SubjectTerms | Adding circuits Circuit design Circuits Computer Imaging Computer Science Computer Systems Organization and Communication Networks Counting circuits Data Structures and Information Theory Design Digital electronics Evolution Evolvable hardware Field programmable gate arrays Gate counting Gates (circuits) Genetic algorithms Genetic Programming Hardware description languages Information Systems and Communication Service Multipliers Operators Original Research Parameterization Parity Pattern Recognition and Graphics Software Engineering/Programming and Operating Systems Vision |
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| Title | Grammatical Evolution of Complex Digital Circuits in SystemVerilog |
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