High-speed, low-complexity systolic designs of novel iterative division algorithms in GF(2/sup m/)

• Published in: IEEE transactions on computers Vol. 53; no. 3; pp. 375 - 380
• Main Authors: Wu, Chien-Hsing, Wu, Chien-Ming, Shieh, Ming-Der, Hwang, Yin-Tsung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Digital arithmetic; Galois fields; Systolic arrays; Very-large-scale integration
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2004.1261843

We extend the binary algorithm invented by Stein and propose novel iterative division algorithms over GF(2/sup m/) for systolic VLSI realization. While algorithm EBg is a basic prototype with guaranteed convergence in at most 2m - 1 iterations, its variants, algorithms EBd and EBdf, are designed for reduced complexity and fixed critical path delay, respectively. We show that algorithms EBd and EBdf can be mapped to parallel-in parallel-out systolic circuits with low area-time complexities of O(m/sup 2/loglogm) and O(m/sup 2/), respectively. Compared to the systolic designs based on the extended Euclid's algorithm, our circuits exhibit significant speed and area advantages.