NEDA: a low-power high-performance DCT architecture

• Published in: IEEE transactions on signal processing Vol. 54; no. 3; pp. 955 - 964
• Main Authors: Shams, A.M., Chidanandan, A., Pan, W., Bayoumi, M.A.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Access methods and protocols, osi model; Adders; Application specific integrated circuits; Applied sciences; Architecture; Arithmetic; Arrays; Complement; Compressing; Costs; Digital signal processing; Digital signal processing chips; Discrete cosine transform (DCT); Discrete cosine transforms; distributed arithmetic; Exact sciences and technology; Hardware; High speed; Information, signal and communications theory; inner product; Mathematical analysis; Miscellaneous; Read only memory; Redundancy; ROM-free multiplication; Signal processing; Signal processing algorithms; Telecommunications; Telecommunications and information theory; Teleprocessing networks. Isdn; Access control; Performance evaluation; Circuit design; Discrete cosine transform (DCT); High precision; Word length; Digital processing; Implementation; ROM-free multiplication; Mathematical analysis; inner product; Discrete cosine transforms; Read only memory(ROM); Redundancy; Finite word; Adder; Power consumption; High power; Simulation; distributed arithmetic; Integrated circuit; Integrated design; Signal processing; Digital signal processor; Comparative study
• ISSN: 1053-587X; 1941-0476
• DOI: 10.1109/TSP.2005.862755

Conventional distributed arithmetic (DA) is popular in application-specific integrated circuit (ASIC) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed, aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in digital signal processing (DSP) applications. Mathematical analysis proves that DA can implement inner product of vectors in the form of two's complement numbers using only additions, followed by a small number of shifts at the final stage. Comparative studies show that NEDA outperforms widely used approaches such as multiply/accumulate (MAC) and DA in many aspects. Being a high-speed architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. A hardware compression scheme is introduced to generate a butterfly structure with minimum number of additions. NEDA-based architectures for 8 /spl times/ 8 discrete cosine transform (DCT) core are presented as an example. Savings exceeding 88% are achieved, when the compression scheme is applied along with NEDA. Finite word-length simulations demonstrate the viability and excellent performance of NEDA.