Synchronous reference frame single-phase phase-locked loop (PLL) algorithm based on half-cycle DFT

• Published in: IET power electronics Vol. 13; no. 9; pp. 1893 - 1900
• Main Authors: Xia, Tao, Zhang, Xu, Tan, Guojun, Liu, Yezhao
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 24.07.2020
• Subjects: advanced phase‐locked loops; discrete Fourier transforms; half‐cycle DFT; HCDFT‐based SRF‐PLL method; high disturbance rejection ability; improved synchronous reference frame phase‐locked loop; phase compensator; phase error; phase locked loops; PLL input signal; Research Article; response time more than one cycle; SDFT‐based PLL; single‐phase power; synchronisation; synchronous reference frame PLL; synchronous reference frame single‐phase phase‐locked loop algorithm; synchronous reference frame single-phase phase-locked loop algorithm; discrete Fourier transforms; response time more than one cycle; improved synchronous reference frame phase-locked loop; SDFT-based PLL; phase error; PLL input signal; synchronisation; half-cycle DFT; phase locked loops; HCDFT-based SRF-PLL method; single-phase power; high disturbance rejection ability; phase compensator; advanced phase-locked loops; synchronous reference frame PLL
• ISSN: 1755-4535; 1755-4543; 1755-4543
• DOI: 10.1049/iet-pel.2019.1542

In single-phase power and energy applications, sliding discrete Fourier transform (SDFT) filter based quadrature signal generation is a well-known tool for designing advanced phase-locked loops (PLLs), particularly for applications where high disturbance rejection ability is demanded. The SDFT-based PLL, nevertheless, has a limited ability in achieving fast response (a response time more than one cycle of the nominal frequency). To deal with this problem, a synchronous reference frame PLL based on half-cycle DFT (HCDFT) is proposed, enabling a fast and accurate synchronisation even in distorted grid. In this study, the fundamental voltage of the PLL input signal is obtained by a HCDFT filter. Then, phase, frequency and amplitude can be detected by the improved synchronous reference frame phase-locked loop (SRF-PLL). Besides, in order to solve the phase error when the frequency changes, a phase compensator is used. The HCDFT-based SRF-PLL method proposed in this study is compared, through experimental results, with a number of conventional methods, showing that the phase can be estimated under grid voltage disturbances accurately and quickly, which verifies the effectiveness and superiority of the proposed algorithm.