Efficient March test algorithm for 1T1R cross-bar with complete fault coverage

• Published in: Electronics letters Vol. 52; no. 18; pp. 1520 - 1522
• Main Authors: Liu, Peng, You, Zhiqiang, Kuang, Jishun, Hu, Zhipeng, Duan, Heng, Wang, Weizheng
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 02.09.2016
• Subjects: 1T1R cross‐bar; Algorithms; Circuits and systems; fault coverage; Faults; integrated circuit testing; March test algorithm; Mathematical analysis; Memory devices; memristor circuits; memristors; nonvolatile memories; one transistor one memristor cross‐bar; pass–fail fault dictionary; resistive RAM; resistive random access memory; Resistors; RRAM; Semiconductor devices; test time overhead; Transistors; Wire; wire interconnection; wires (electric); memristors; resistive random access memory; RRAM; fault coverage; wires (electric); integrated circuit testing; one transistor one memristor cross-bar; March test algorithm; wire interconnection; 1T1R cross-bar; nonvolatile memories; resistive RAM; test time overhead; pass–fail fault dictionary; memristor circuits
• ISSN: 0013-5194; 1350-911X; 1350-911X
• DOI: 10.1049/el.2016.1693

As an attractive option of future non-volatile memories, resistive RAM (RRAM) has attracted more attentions. Among RRAM architectures, one transistor one memristor (1T1R) cross-bar is the most fledged one. A March C*-1T1R algorithm is proposed for 1T1R cross-bar. The pass–fail fault dictionary of the proposed March test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors, transistors and their interconnecting wires with a little test time overhead compared with previous methods.