Versatile digital architecture for mobile terminal

• Published in: Microprocessors and microsystems Vol. 39; no. 6; pp. 405 - 417
• Main Authors: Benhaoues, A., Toumi, S., Tanougast, C., Bourennane, E., Messaoudi, K., Mayache, H.
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.08.2015; Elsevier
• Series: Microprocessors & Microsystems
• Subjects: Algorithms; Architecture; Architecture (computers); Common Operators technique; Computer Science; Cordic algorithm; Digital; Electronics; Embedded Systems; Engineering Sciences; FFT-SDF; Field programmable gate arrays; Generic hardware architectures; Mathematical analysis; Mathematical models; Optimized architectural synthesis; Rake receiver; Terminals; FFT-SDF; Cordic algorithm; Optimized architectural synthesis; Common Operators technique; Rake receiver; Generic hardware architectures
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2015.05.008

Nowadays, modern communication systems require higher data throughput to transmit increasing flow of data. Since mobile terminal needs to support multiple radio technologies, the current challenge is to design and engineering of new digital and adaptive generic architectures. In addition these versatile architectures are able to take over of many functions, which leads to avoid the use of many circuits for these different functions. In this paper, we have identified similarities between the despreader unit in Rake receiver, the FFT-SDF (Fast Fourier Transform-Single path Delay Feedback) and the Cordic (Coordinate Rotation Digital Computer) algorithm to propose a generic architecture shared between these three widely used algorithms (architectural synthesis based on common operators technique). The proposed synthesizable architecture is coded using VHDL onto a Virtex-5 Field-Programmable Gate Array (FPGA) device and results are compared with FPGA implementations of similar works that share some common functionality. The implementation demonstrates that the proposed architecture can deliver a high reduction of the FPGA logic requirements with high maximum work frequency.