Application of the residue number system to reduce hardware costs of the convolutional neural network implementation

• Published in: Mathematics and computers in simulation Vol. 177; pp. 232 - 243
• Main Authors: Valueva, M.V., Nagornov, N.N., Lyakhov, P.A., Valuev, G.V., Chervyakov, N.I.
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.11.2020
• Subjects: Convolutional neural networks; Field-programmable gate array (FPGA); Image processing; Quantization noise; Residue number system; Quantization noise; Residue number system; Image processing; Field-programmable gate array (FPGA); Convolutional neural networks
• ISSN: 0378-4754; 1872-7166
• DOI: 10.1016/j.matcom.2020.04.031

Convolutional neural networks are a promising tool for solving the problem of pattern recognition. Most well-known convolutional neural networks implementations require a significant amount of memory to store weights in the process of learning and working. We propose a convolutional neural network architecture in which the neural network is divided into hardware and software parts to increase performance and reduce the cost of implementation resources. We also propose to use the residue number system (RNS) in the hardware part to implement the convolutional layer of the neural network. Software simulations using Matlab 2018b showed that convolutional neural network with a minimum number of layers can be quickly and successfully trained. The hardware implementation of the convolution layer shows that the use of RNS allows to reduce the hardware costs on 7.86%–37.78% compared to the two’s complement implementation. The use of the proposed heterogeneous implementation reduces the average time of image recognition by 41.17%.