Constructing Edge-Colored Graph for Heterogeneous Networks
In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malf...
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| Published in | Journal of computer science and technology Vol. 30; no. 5; pp. 1154 - 1160 |
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| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
New York
Springer US
01.09.2015
Springer Nature B.V |
| Subjects | |
| Online Access | Get full text |
| ISSN | 1000-9000 1860-4749 |
| DOI | 10.1007/s11390-015-1551-0 |
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| Abstract | In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malfunction. We propose an approach to designing such networks under arbitrary parameters. We also show that the proposed approach can be used to optimize inter-router connections in network-on-chip to reduce the additional consum!otion of energy and time delay. |
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| AbstractList | In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malfunction. We propose an approach to designing such networks under arbitrary parameters. We also show that the proposed approach can be used to optimize inter-router connections in network-on-chip to reduce the additional consumption of energy and time delay. In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malfunction. We propose an approach to designing such networks under arbitrary parameters. We also show that the proposed approach can be used to optimize inter-router connections in network-on-chip to reduce the additional consum!otion of energy and time delay. |
| Author | 侯睿 武继刚 陈亚文 张海波 隋秀峰 |
| AuthorAffiliation | School of Computer Science and Software Engineering, Tianjin Polytechnic University, Tianjin 300387, China State Key Laboratory of Computer Architecture~ Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China Department of Computer Science, University of Otago, Dunedin 9054, New Zealand |
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| Cites_doi | 10.1016/j.comcom.2013.11.005 10.1016/j.ipl.2011.03.017 10.1017/CBO9780511804090 10.1007/s00026-005-0247-5 10.1038/srep05034 10.1364/OFC.2009.OTuI4 10.1109/ISIT.2013.6620241 10.1109/NOCS.2008.4492725 10.1109/DATE.2004.1269002 |
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| Copyright | Springer Science+Business Media New York 2015 Springer Science+Business Media New York 2015. Copyright © Wanfang Data Co. Ltd. All Rights Reserved. |
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| DOI | 10.1007/s11390-015-1551-0 |
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| Keywords | network-on-chip fault tolerance homogeneous fault reconfigurable system network reliability |
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| Notes | In order to build a fault-tolerant network, heterogeneous facilities are arranged in the network to prevent homogeneous faults from causing serious damage. This paper uses edge-colored graph to investigate the features of a network topology which is survivable after a set of homogeneous devices malfunction. We propose an approach to designing such networks under arbitrary parameters. We also show that the proposed approach can be used to optimize inter-router connections in network-on-chip to reduce the additional consum!otion of energy and time delay. 11-2296/TP Rui Hou, Ji-Gang Wu , Yawen Chen, Haibo Zhang, and Xiu-Feng Sui（1 School of Computer Science and Software Engineering, Tianjin Polytechnic University, Tianjin 300387, China 2State Key Laboratory of Computer Arehitecture~ Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China 3Department of Computer Science, University of Otago, Dunedin 9054, New Zealand） network reliability； homogeneous fault； fault tolerance； reconfigurable system； network-on-chip ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 content type line 23 |
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| SubjectTerms | Algorithms Artificial Intelligence Communication Computer networks Computer Science Computers Construction Data Structures and Information Theory Design Energy consumption Fault tolerance Faults Graph coloring Graphs Information Systems Applications (incl.Internet) Joints Laboratories Network topologies Networks Regular Paper Software Engineering Software reliability Studies System on chip Theory of Computation Time delay Windows operating system 容错网络 异构网络 时间延迟 构造 着色图 网络拓扑 设备故障 路由器 |
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| Title | Constructing Edge-Colored Graph for Heterogeneous Networks |
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