Optimized Algorithms and Hardware Implementation of Median Filter for Image Processing

• Published in: Circuits, systems, and signal processing Vol. 42; no. 9; pp. 5545 - 5558
• Main Authors: Draz, H. H., Elashker, N. E., Mahmoud, Mervat M. A.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.09.2023; Springer Nature B.V
• Subjects: Algorithms; Artificial neural networks; Circuits and Systems; Digital imaging; Electrical Engineering; Electronics and Microelectronics; Embedded systems; Engineering; Field programmable gate arrays; Image filters; Image processing; Instrumentation; Microprocessors; Parallel processing; Signal,Image and Speech Processing; Median of medians; Embedded systems; Image de-noising; FPGA; Median filter
• ISSN: 0278-081X; 1531-5878; 1531-5878
• DOI: 10.1007/s00034-023-02370-x

Image processing algorithms are essential for clarifying the image and improving the ability to recognize distinct characteristics of the image. The field of digital image processing is widespread in several research and technology applications. In many of these applications, the existence of impulsive noise in the obtained images is one of the most frequent problems. The median filter is a strong method to remove the impulsive noise; it effectively eliminates salt and pepper noise from the image. The main target of this paper is to investigate efficient median filter units to be connected to a general-purpose processor (GPP) for FPGA-based embedded systems. The paper exposes three novel techniques, two of them specially for median filtering techniques and the third one is used to get the maximum number of any 9 elements array. The proposed algorithms are inspired by the Median Of Median (MOM) algorithm. The first two techniques are tested for filtering 3 × 3 image windows and optimized for producing the expected result in high accuracy, short time, and reduced number of comparisons. The last technique is tested for a 9 elements array for extracting the maximum number in same high efficiency manner. Furthermore, the three proposed techniques are implemented leveraging the advantage of the parallel processing and the FPGA flexible resources to satisfy the real-time processing constraints. A comparison between the first two proposed filtering units and their counterparts in the literature is included. The comparison reveals the superiority of the first technique in terms of accuracy with fewer comparators than previously published techniques. Besides, the paper illustrates how the concept beyond the proposed techniques can be used to perform the maximum pooling for convolution neural networks.