Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA

• Published in: Chronic diseases and translational medicine Vol. 11; no. 4; pp. 149 - 158
• Main Authors: Zhang, Hao, Chen, Dongdong, Ko, Seok-Bum
• Format: Journal Article
• Language: English
• Published: Beijing The Institution of Engineering and Technology 01.07.2017; John Wiley & Sons, Inc
• Subjects: Algorithms; Altera Arria‐10 devices; ASIC platform; Case studies; Design; double‐precision operations; DSP blocks; field programmable gate array; Field programmable gate arrays; floating point arithmetic; floating‐point multiplication; Fourier transforms; Intellectual property; iterative methods; Karatsuba algorithm; Linear algebra; Multiplication & division; pipeline registers; power‐efficient iterative FP multiplier architecture; Research Article; single‐precision operations; Virtex‐5 devices; Xilinx Virtex‐7; iterative methods; field programmable gate arrays; pipeline registers; power-efficient iterative FP multiplier architecture; floating point arithmetic; double-precision operations; Karatsuba algorithm; Xilinx Virtex-7; floating-point multiplication; Virtex-5 devices; field programmable gate array; single-precision operations; Altera Arria-10 devices; DSP blocks; ASIC platform
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2016.0100

In this study, an area and power-efficient iterative floating-point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single-precision (SP) and double-precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look-up tables (LUTs), and 31.2% less flip-flops while having 4% faster clock frequency on Virtex-5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower-power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex-7 and Altera Arria-10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM-90 nm ASIC platform are reported.