Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 11; pp. 2300 - 2313
• Main Authors: Reis, Dayane, Takeshita, Jonathan, Jung, Taeho, Niemier, Michael, Hu, Xiaobo Sharon
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Architecture; Central Processing Unit; Central processing units; Circuits; Cloud computing; CMOS; Computer architecture; computing-in-memory (CiM); CPUs; Data transfer; encrypted data processing; Encryption; Energy; Field programmable gate arrays; homomorphic encryption (HE); Sense amplifiers; Static random access memory; Task analysis
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2020.3017595

Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory processing (NMP) and computing-in-memory (CiM)-paradigms where computation is done within the memory boundaries-represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications, such as HE. This article introduces CiM-HE, a CiM architecture that can support operations for the Brakerski/Fan-Vercauteren (B/FV) scheme, a somewhat HE scheme for general computation. CiM-HE hardware consists of customized peripherals, such as sense amplifiers, adders, bit shifters, and sequencing circuits. The peripherals are based on CMOS technology and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against: 1) two optimized CPU HE implementations and 2) a field-programmable gate array (FPGA)-based HE accelerator implementation. Compared with a CPU solution, CiM-HE obtains speedups between <inline-formula> <tex-math notation="LaTeX">4.6\times </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">9.1\times </tex-math></inline-formula> and energy savings between <inline-formula> <tex-math notation="LaTeX">266.4\times </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">532.8\times </tex-math></inline-formula> for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-to-end tasks, i.e., mean, variance, linear regression, and inference, are up to <inline-formula> <tex-math notation="LaTeX">1.1\times </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">7.7\times </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">7.1\times </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">7.5\times </tex-math></inline-formula> faster (and <inline-formula> <tex-math notation="LaTeX">301.1\times </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">404.6\times </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">532.3\times </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">532.8\times </tex-math></inline-formula> more energy efficient). Compared with CPU-based HE in previous work, CiM-HE obtains <inline-formula> <tex-math notation="LaTeX">14.3\times </tex-math></inline-formula> speedup and <inline-formula> <tex-math notation="LaTeX">> 2600\times </tex-math></inline-formula> energy savings. Finally, our design offers <inline-formula> <tex-math notation="LaTeX">2.2\times </tex-math></inline-formula> speedup with <inline-formula> <tex-math notation="LaTeX">88.1\times </tex-math></inline-formula> energy savings compared with a state-of-the-art FPGA-based accelerator.