Statistical Strategies to Reproduce the Propagation Delay Time Variability Using Compact Models

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 66; no. 11; pp. 1880 - 1884
• Main Authors: Jooypa, Hamed, Dideban, Daryoosh
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; CMOS; Compact model; Correlation; Correlation coefficient; Correlation coefficients; Delay time; Integrated circuit modeling; Logic gates; Mathematical models; nano-CMOS; parameter reproduction; Parameters; Propagation; Propagation delay; propagation delay time; Semiconductor device modeling; statistical variability; Strategy
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2019.2895364

In this brief, we propose three different strategies to estimate the propagation delay time of a nano-CMOS inverter subject to statistical variability. Based on statistical distribution of efficient parameters in the selected compact model, we have reproduced these parameters taking their statistical behavior into account. Since mean and standard deviation (SD) of each parameter and correlation coefficient between parameter pairs are important figures of merit, three strategies are proposed and the accuracies of obtained results using them are evaluated. The first strategy replicates the mean and SD of original parameters but ignores the correlations between them. The second strategy takes mean, SD and the highest correlation coefficient into account while the third strategy considers all of correlations as well as mean and SD of parameters. While the introduced error in the mean of propagation delay time remains negligible between these strategies, the error in the SD can be reached to 16%, 6%, and 3% for no correlation, partial correlation, and full correlation strategies, respectively.