An Arbitrary-Phase-Varying Digital Chirp Signal Generator Based on Improved CORDIC Algorithm and Trajectory Approximator

• Published in: IEEE access Vol. 12; pp. 135362 - 135371
• Main Authors: Zhang, Haoran, Chen, Minqi, Wan, Shuqin, Jiao, Zihao, Hu, Shenglin, Song, Peng
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Approximation algorithms; Chirp; Chirp signals; discrete-time PID controller; Field programmable gate arrays; finite state machine (FSM); Finite state machines; FPGA; Logic; Logic circuits; neural network; Pulse duration; Radar antennas; Radar equipment; Scaling-free coordinate rotation digital computer (CORDIC) algorithm; Signal generators; Table lookup; Trajectory
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3456554

The digital chirp signal (DCS) is commonly used in modern radar system and ultrashort pulse application. The traditional method is using DDS device, but this method is limited by many restrictions, including device limit, cost limit and application range. In consideration of those restrictions, we propose a new method implemented on field programmable gate array (FPGA). It has a composite architecture featuring an improved CORDIC algorithm core to generate arbitrary-phase-varying DCS and a trajectory approximator to eliminate uncertain error. The improved CORDIC algorithm core is embedded in a finite state machine (FSM) which make the design more efficient. Meanwhile, the trajectory approximator is used to counteract the uncertainty influence from the output error and disturbance. An experiment is built for the efficiency and validation of the proposed method. We generated a DCS with frequency bandwidth of 1.25MHz, starting from 0Hz to 1.25MHz and its pulse duration is 81.92us. Another experiment is done to validate the feasibility generating nonlinear phase chirp digital signal. According to the results of the practical implementation in FPGA, the main advantage of the proposed technique is that it can reduce the usage of Memory, Slice Register and Logic gates of FPGA.