Recent Advances of High-Speed Short-Reach Optical Interconnects for Data Centers

• Published in: IEEE open journal of solid-state circuits Vol. 5; pp. 86 - 100
• Main Authors: Zhang, Chongyun, Chen, Fuzhan, Wang, Li, Wang, Lin, Patrick Yue, C.
• Format: Journal Article
• Language: English
• Published: New York IEEE 2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Clock and data recovery (CDR); Clock recovery; Clocks; Compensation; Computer architecture; Computer centers; data center interconnect; Data centers; Data recovery; Density; four-level pulse amplitude modulation (PAM-4); High-speed optical techniques; Noise reduction; Optical fiber communication; Optical interconnections; Optical interconnects; optical receiver; Optical receivers; Optical transmitters; Phase locked loops; Phase noise; phase-locked loop (PLL); Power efficiency; Signal integrity; Signal quality; transmitter; Vertical cavity surface emission lasers; Vertical cavity surface emitting lasers; vertical-cavity surface-emitting laser (VCSEL); Vibration
• ISSN: 2644-1349; 2644-1349
• DOI: 10.1109/OJSSCS.2025.3526132

The ever-increasing demand for data centers and high-performance computing systems necessitate power-efficient, low-latency, and high-density interconnect design. This article reviews and analyzes recent design challenges and advances of optical transceiver, phase-locked loop (PLL), and clock and data recovery (CDR) for data center applications with a distance of ~100 m. At the transmitter side, nonidealities of the widely used vertical-cavity surface-emitting laser (VCSEL) are described, followed by reviews on existing compensation techniques for those nonidealities. At the receiver side, tradeoffs between gain, bandwidth (BW), noise, and linearity in PAM-4 optical receiver design are introduced, and design methods to improve the power efficiency and BW density are particularly discussed. Regarding clock generation which directly affects the performance of the transceiver, compact PLL design techniques focusing on in-band phase noise reduction and low-jitter performance are described. The signal integrity of PAM-4 signal becomes more susceptible to noise and jitter due to reduced signal level spacing. To address the uncorrelated jitter accumulation within the CDR which limits the signal quality and transmission distance, jitter compensation schemes in CDR design are described. And the clock distribution techniques for multilane transceiver systems are discussed.