A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications - MIN, Young-Jae; JEONG, Chan-Hui; KIM, Kyu-Young; WON HO CHOI; SON, Jong-Pil; KIM, Chulwoo; KIM, Soo-Won (IEEE transactions on very large scale integration (VLSI) systems, 2012)
Keywords: Applied sciences; Approximation; Circuits; Clocks; CMOS; Delay lines; Design. Technologies. Operation analysis. Testing; Detectors; Double data rate (DDR); DRAM; duty-cycle corrector (DCC); Electronics; Error analysis; Errors; Exact sciences and technology; General equipment and techniques; Generators; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuits; Integrated circuits by function (including memories and processors); Mathematical analysis; Physics; Random access memory; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing; Solid state circuits; successive approximation register (SAR) controller; Very large scale integration; Double data rate (DDR); Die; duty-cycle corrector (DCC); Random access memory; Control system; Measurement sensor; Output circuit; Output signal; Implementation; Search algorithm; Register file; Successive approximation; successive approximation register (SAR) controller; Non volatile memory; Complementary MOS technology; Integrated circuit; DRAM; Separator circuit; Dynamic random access memory