A 6.4 Gbit/s Embedded Compression Codec for Memory-Efficient Applications on Advanced-HD Specification

• Published in: IEEE transactions on circuits and systems for video technology Vol. 20; no. 10; pp. 1277 - 1291
• Main Authors: Tsai, Tsung-Han, Lee, Yu-Hsuan
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Applied sciences; Bandwidth; Binary codes; Capacity planning; Circuit properties; CMOS technology; Codec; Codecs; Coding; Coding, codes; Compressing; Computational efficiency; Context modeling; Displays; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; embedded compression (EC); Entropy; Entropy coding; Exact sciences and technology; High speed; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); lossless/near-lossless compression; Memory; Parallel processing; rate control; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Signal and communications theory; Signal convertors; Solid modeling; Specifications; Systems, networks and services of telecommunications; Telecommunications; Telecommunications and information theory; Transmission and modulation (techniques and equipments); very large scale integration (VLSI) architecture; Display equipment; Performance evaluation; Geometric codes; embedded compression (EC); Binary code; Modeling; Adaptive method; Implementation; Geometrical model; Image coding; Codec; Traffic control; Content analysis; High rate transmission; very large scale integration (VLSI) architecture; VLSI circuit; Flow rate regulation; Entropy codes; Teletraffic; Image compression; Specification; Frame rate; Algorithm; Information transmission; Adaptive coding; Storage management; lossless/near-lossless compression; Memory capacity; Context-modeling; rate control; Open market
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2010.2057770

The embedded compression (EC) technique is applied to reduce the memory bandwidth and capacity in a display system. In this paper, the high-speed EC algorithm is proposed for advanced-HD specification. It mainly comprises three features: 1) the associated geometric-based probability model is developed to construct context-modeling mechanism without context-table; 2) develop content-adaptive Golomb-Rice code and geometric-based binary code as the entropy coding with minor order of context; and 3) provide the rate control mechanism to guarantee the saving ratio of memory bandwidth and capacity. With competitive coding efficiency, the computation-efficiency of the proposed EC algorithm is about 44% and 40% of FELICS and JPEG-LS. The proposed very-large-scale integration architecture of entire codec is implemented in TSMC 0.18- 1P6M CMOS technology. Based on pixel-based parallelism and segment-based parallelism techniques, the encoding/decoding capability reaches Quad Full-high definition (QFHD) (3840 × 2160) at 30 Hz. The maximum throughput is as high as 6.4 Gbit/s. Furthermore, with multi-level parallelism, the performance can be extended to QHD (2560 × 1440) at 120 Hz and QFHD at 120 Hz for the double frame rate technique.