A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 19; no. 6; pp. 953 - 962
• Main Authors: Basu, Arindam, Hasler, Paul E
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.06.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Analog circuits; Analog-digital conversion; Applied sciences; Circuit noise; Circuit properties; Current measurement; Drains; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Field programmable gate arrays; Floating-gate programming; floating-point analog-to-digital converter (ADC); Gate arrays; Gates; hot-electron injection; Integrated circuits; Integrated circuits by function (including memories and processors); logarithmic compression; low power; Modulation; programmable analog; Programming; Pulse modulation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Signal convertors; System-on-a-chip; Temperature measurement; Topology; Velocity measurement; Very large scale integration; Voltage; Gate current; Logarithmic amplifier; Adaptive method; Floating gate technology; hot-electron injection; Analog converter; logarithmic compression; AD converter; Transimpedance; Nominal value; Floating point; Hot electron; floating-point analog-to-digital converter (ADC); Operational amplifier; Gate voltage; programmable analog; Electron injection; Field programmable gate array; DA converter; Algorithm; Temperature measurement; Floating-gate programming; Integrated circuit; Drain voltage; low power; Thermal noise; Microprocessor; Pulse duration modulation
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2010.2042626

This paper presents an on-chip system with digital serial peripheral interface (SPI) interface that enables accurate programming of floating gate arrays at a high speed. The main component allowing this speedup is a floating point current measuring analog-to-digital convertor (ADC). The ADC comprises a wide range logarithmic transimpedance amplifier (TIA) followed by a linear ramp ADC. The TIA operates over seven decades of current going down to sub-pA levels. It incorporates an adaptive biasing scheme to save power. The topology provides a relatively temperature independent measurement of the floating-gate voltage. The TIA-ADC combination operates over six decades at a thermal noise limited accuracy of 9.5 bits when average conversion time is around 500 μs. The system features level-shifters and selection circuitry at the periphery of the floating gate array, current-steering digital-to-analog converters (DACs) to set gate and drain voltages, and SPI for a microprocessor or field-programmable gate array (FPGA). Algorithms using either pulse-width modulation or drain voltage modulation can be implemented on this platform. We present data for this system from 0.5 μm AMI and 0.35 μ m TSMC processes.