Integrated Phase-Locking Scheme for SDFT-Based Harmonic Analysis of Periodic Signals

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 55; no. 1; pp. 51 - 55
• Main Authors: Sumathi, P., Janakiraman, P.A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuits; Discrete Fourier transforms; Finite impulse response filter; Fourier analysis; Fourier transforms; Frequency drift; Frequency estimation; Harmonic analysis; Locks; On-line systems; phase error; Phase locked loops; phase-locked loop (PLL); Power harmonic filters; Resonator filters; Sampling; Sampling methods; Signal design; sliding discrete Fourier transform (SDFT); Steady-state; Time functions
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2007.907854

The sliding discrete Fourier transform splits periodic signals into selected harmonic components, as on-line time functions. Ordinarily, the sampling frequency is equal to the product of the nominal signal frequency and the window width N. However, when the signal frequency drifts, to avoid the phase and magnitude errors, the sampling frequency can be adaptively adjusted using the phase-error itself. An integrated phase-locked loop scheme and its parameters like hold-in, pull-in ranges, lock time, steady-state