A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links
Fractionally spaced linear receive equalization (FSE) is shown in this work as an effective method to perform joint equalization and phase-synchronization in mesochronous high-speed links. Given an arbitrary receive sampling phase, a modified sign-sign least mean squares (M-SSLMS) adaptive algorithm...
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| Published in | IEEE journal of solid-state circuits Vol. 46; no. 5; pp. 1183 - 1197 |
|---|---|
| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
New York, NY
IEEE
01.05.2011
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| Online Access | Get full text |
| ISSN | 0018-9200 1558-173X |
| DOI | 10.1109/JSSC.2011.2105670 |
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| Abstract | Fractionally spaced linear receive equalization (FSE) is shown in this work as an effective method to perform joint equalization and phase-synchronization in mesochronous high-speed links. Given an arbitrary receive sampling phase, a modified sign-sign least mean squares (M-SSLMS) adaptive algorithm is developed to tune the FSE tap weights to mitigate the inter-symbol interference (ISI), avoiding the divergence issue in the standard sign-sign least mean squares (SSLMS) algorithm. To achieve the desired linearity with good energy efficiency and large input dynamic range, an FSE is implemented using a voltage-time conversion technique by inverter-based threshold detectors with auto-zeroing function. The two-tap quad-rate FSE receiver with one-tap DFE is fabricated in 90 nm bulk CMOS technology, occupying 0.03 mm 2 active area. With a 1.2 V supply, it achieves a 6.25 Gb/s rate, 3.6 mW/Gb/s efficiency and over 4 bits of linearity. |
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| AbstractList | Fractionally spaced linear receive equalization (FSE) is shown in this work as an effective method to perform joint equalization and phase-synchronization in mesochronous high-speed links. Given an arbitrary receive sampling phase, a modified sign-sign least mean squares (M-SSLMS) adaptive algorithm is developed to tune the FSE tap weights to mitigate the inter-symbol interference (ISI), avoiding the divergence issue in the standard sign-sign least mean squares (SSLMS) algorithm. To achieve the desired linearity with good energy efficiency and large input dynamic range, an FSE is implemented using a voltage-time conversion technique by inverter-based threshold detectors with auto-zeroing function. The two-tap quad-rate FSE receiver with one-tap DFE is fabricated in 90 nm bulk CMOS technology, occupying 0.03 mm[Formula Omitted] active area. With a 1.2 V supply, it achieves a 6.25 Gb/s rate, 3.6 mW/Gb/s efficiency and over 4 bits of linearity. Fractionally spaced linear receive equalization (FSE) is shown in this work as an effective method to perform joint equalization and phase-synchronization in mesochronous high-speed links. Given an arbitrary receive sampling phase, a modified sign-sign least mean squares (M-SSLMS) adaptive algorithm is developed to tune the FSE tap weights to mitigate the inter-symbol interference (ISI), avoiding the divergence issue in the standard sign-sign least mean squares (SSLMS) algorithm. To achieve the desired linearity with good energy efficiency and large input dynamic range, an FSE is implemented using a voltage-time conversion technique by inverter-based threshold detectors with auto-zeroing function. The two-tap quad-rate FSE receiver with one-tap DFE is fabricated in 90 nm bulk CMOS technology, occupying 0.03 mm 2 active area. With a 1.2 V supply, it achieves a 6.25 Gb/s rate, 3.6 mW/Gb/s efficiency and over 4 bits of linearity. |
| Author | Stojanović, V Sanquan Song |
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| Keywords | Performance evaluation Inverter Dynamic response voltage-time conversion technique Adaptive algorithm Phase synchronization high-speed links modified sign-sign LMS algorithm Measurement sensor Fractionally spaced linear receive equalization Receiver Decision feedback equalizers Intersymbol interference Energetic efficiency Complementary MOS technology Sampling Ecological approach Design for environment Least mean squares methods |
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| SubjectTerms | Algorithms Applied sciences Approximation algorithms Conversion Decision feedback equalizers Design. Technologies. Operation analysis. Testing Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Equalization Exact sciences and technology Fractionally spaced linear receive equalization General equipment and techniques High speed high-speed links Instruments, apparatus, components and techniques common to several branches of physics and astronomy Integrated circuits Least mean squares Least mean squares algorithm Least squares approximation Linearity Links modified sign-sign LMS algorithm Physics Quantization Receivers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing Synchronization voltage-time conversion technique |
| Title | A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links |
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