A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 12; pp. 2842 - 2851
• Main Authors: Gupta, M., Bang-Sup Song
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.12.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bandwidth; Calibration; Charge pumps; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clocks; Consumption; Correlation; Delta-sigma modulation; Digital-analog conversion; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; fractional- N frequency synthesizers; Frequency synthesizers; Gain; Integrated circuits; Integrated circuits by function (including memories and processors); Least squares approximation; Noise; Oscillators, resonators, synthetizers; Phase locked loops; Phase noise; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Signal to noise ratio; spur cancellation; Synthesizers; Wideband; Phase noise; Performance evaluation; fractional-N frequency synthesizers; Second order; Arithmetic circuit; Noise reduction; Delta-sigma modulation; DA converter; Clock; Algorithm; N order; Frequency synthesizer; Phase locked loop; Sigma-delta modulation; AD converter; Complementary MOS technology; spur cancellation; Integrated circuit; Correlation function; Charge pumping; phase-locked loops; Divider; Gain; Least mean squares methods
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.884829

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm 2 , and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power