More efficient systolic arrays for multiplication in GF( 2 m ) using LSB first algorithm with irreducible polynomials and trinomials

• Published in: Computers & electrical engineering Vol. 35; no. 1; pp. 159 - 167
• Main Authors: Kwon, Soonhak, Kim, Chang Hoon, Hong, Chun Pyo
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 2009
• Subjects: Finite field arithmetic; LSB first algorithm; Systolic array; Trinomial; VLSI; Systolic array; LSB first algorithm; VLSI; Finite field arithmetic; Trinomial
• ISSN: 0045-7906; 1879-0755
• DOI: 10.1016/j.compeleceng.2008.09.009

Systolic arrays for multiplication in GF ( 2 m ) of Yeh et al. with LSB (least significant bit) first algorithm have the unfavorable properties such as increased area complexity and bidirectional data flows compared with the arrays of Wang and Lin with MSB (most significant bit) first algorithm. In this paper, by using a polynomial basis with LSB first algorithm, we present new bit parallel and bit serial systolic arrays over GF ( 2 m ) . Our bit parallel systolic multiplier has unidirectional data flows with seven latches in each basic cell. Also our bit serial systolic array has only one control signal with eight latches in each basic cell. Thus our new arrays with LSB first algorithm have shorter critical path delay, comparable hardware complexity, and have the same unidirectional data flows compared with the arrays using MSB first algorithm. We also present new linear systolic arrays for multiplication in GF ( 2 m ) using irreducible trinomial x m + x k + 1 . It is shown that our linear arrays with trinomial basis have reduced hardware complexity since they require two fewer latches than the linear systolic arrays using general irreducible polynomials.