Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain...

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Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 23; no. 7; pp. 1142 - 1153
Main Authors Rosinger, P., Al-Hashimi, B.M., Nicolici, N.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.07.2004
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN0278-0070
1937-4151
DOI10.1109/TCAD.2004.829797

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Abstract Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2%-3%). An algorithmic procedure for assigning flip-flops to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak-power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and, respectively, maximum number of simultaneous transitions.
AbstractList Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2%-3%). An algorithmic procedure for assigning flip-flops to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak-power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and, respectively, maximum number of simultaneous transitions.
While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms.
Author Rosinger, P.
Nicolici, N.
Al-Hashimi, B.M.
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Snippet Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently...
While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan...
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SubjectTerms Activation
Algorithms
Architecture
Automatic test pattern generation
Automatic testing
Circuit testing
Clocks
Density
Design engineering
Flip-flops
Logic testing
Partitioning algorithms
Power dissipation
Reduction
Segments
Studies
Switches
Voltage
Title Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction
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