Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures

• Published in: IEEE transactions on signal processing Vol. 54; no. 11; pp. 4419 - 4434
• Main Authors: Chao Cheng, Parhi, K.K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Applied sciences; Array signal processing; Convolution; Costs; Cyclic convolution; Discrete cosine transforms; Exact sciences and technology; Hardware; High speed; Information, signal and communications theory; Integrated circuits; Large scale integration; linear convolution; Miscellaneous; Signal processing; Signal processing algorithms; Studies; Systolic arrays; Telecommunications and information theory; Very large scale integration; VLSI circuit; Information rate; Systolic network; Information transmission; Implementation; Periodic structure; Cyclic system; Convolution; linear convolution; very large-scale integration; Signal processing; Cyclic convolution; Fast algorithm; Delay line; Discrete cosine transforms
• ISSN: 1053-587X; 1941-0476
• DOI: 10.1109/TSP.2006.881269

Cyclic convolution is a widely used operation in signal processing. In very large-scale integration (VLSI) design, it is usually implemented with systolic array and distributed arithmetic; however, these implementation designs may not be fast enough or use too much hardware cost when the convolution length is large. This paper presents a new fast cyclic convolution algorithm, which is hardware efficient and suitable for high-speed VLSI implementation, especially when the convolution length is large. For example, when the proposed fast cyclic convolution algorithm is applied to the implementation of prime length discrete cosine transform (DCT), the proposed high-throughput implementation of 1297-length DCT design saves 1216 (94%) multiplications, 282 (22%) additions, and 4792 (74%) delay elements compared with those of recently proposed systolic array based algorithms. Furthermore, the proposed algorithm can run at a speed that is 1.5 times that of previous designs and requires less I/O cost as long as the wordlength L is less than 20 bits