Parallelization of Full Search Motion Estimation Algorithm for Parallel and Distributed Platforms
This work presents an efficient method to map the Full Search algorithm for Motion Estimation (ME) onto General Purpose Graphic Processing Unit (GPGPU) architectures using Compute Unified Device Architecture (CUDA) programming model. Our method jointly exploits the massive parallelism available in c...
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| Published in | International journal of parallel programming Vol. 42; no. 2; pp. 239 - 264 |
|---|---|
| Main Authors | , , , , , |
| Format | Journal Article |
| Language | English |
| Published |
Boston
Springer US
01.04.2014
Springer Nature B.V |
| Subjects | |
| Online Access | Get full text |
| ISSN | 0885-7458 1573-7640 |
| DOI | 10.1007/s10766-012-0216-7 |
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| Abstract | This work presents an efficient method to map the
Full Search
algorithm for Motion Estimation (ME) onto General Purpose Graphic Processing Unit (GPGPU) architectures using Compute Unified Device Architecture (CUDA) programming model. Our method jointly exploits the massive parallelism available in current GPGPU devices and the parallelism potential of
Full Search
algorithm. Our main goal is to evaluate the feasibility of video codecs implementation using GPGPUs and its advantages and drawbacks compared to other platforms. Therefore, for comparison reasons, three solutions were developed using distinct programming paradigms for distinct underlying hardware architectures: (i) a sequential solution for general-purpose processor (GPP); (ii) a parallel solution for multi-core GPP using OpenMP library; (iii) a distributed solution for cluster/grid machines using Message Passing Interface (MPI) library. The CUDA-based solution for GPGPUs achieves speed-up compatible to the indicated by the theoretical model for different search areas. Our GPGPU
Full Search
Motion Estimation provides 2×, 20× and 1664× speed-up when compared to MPI, OpenMP and sequential implementations, respectively. Compared to state-of-the-art, our solution reaches up to 17× speed-up. |
|---|---|
| AbstractList | This work presents an efficient method to map the Full Search algorithm for Motion Estimation (ME) onto General Purpose Graphic Processing Unit (GPGPU) architectures using Compute Unified Device Architecture (CUDA) programming model. Our method jointly exploits the massive parallelism available in current GPGPU devices and the parallelism potential of Full Search algorithm. Our main goal is to evaluate the feasibility of video codecs implementation using GPGPUs and its advantages and drawbacks compared to other platforms. Therefore, for comparison reasons, three solutions were developed using distinct programming paradigms for distinct underlying hardware architectures: (i) a sequential solution for general-purpose processor (GPP); (ii) a parallel solution for multi-core GPP using OpenMP library; (iii) a distributed solution for cluster/grid machines using Message Passing Interface (MPI) library. The CUDA-based solution for GPGPUs achieves speed-up compatible to the indicated by the theoretical model for different search areas. Our GPGPU Full Search Motion Estimation provides 2×, 20× and 1664× speed-up when compared to MPI, OpenMP and sequential implementations, respectively. Compared to state-of-the-art, our solution reaches up to 17× speed-up.[PUBLICATION ABSTRACT] This work presents an efficient method to map the Full Search algorithm for Motion Estimation (ME) onto General Purpose Graphic Processing Unit (GPGPU) architectures using Compute Unified Device Architecture (CUDA) programming model. Our method jointly exploits the massive parallelism available in current GPGPU devices and the parallelism potential of Full Search algorithm. Our main goal is to evaluate the feasibility of video codecs implementation using GPGPUs and its advantages and drawbacks compared to other platforms. Therefore, for comparison reasons, three solutions were developed using distinct programming paradigms for distinct underlying hardware architectures: (i) a sequential solution for general-purpose processor (GPP); (ii) a parallel solution for multi-core GPP using OpenMP library; (iii) a distributed solution for cluster/grid machines using Message Passing Interface (MPI) library. The CUDA-based solution for GPGPUs achieves speed-up compatible to the indicated by the theoretical model for different search areas. Our GPGPU Full Search Motion Estimation provides 2, 20 and 1664 speed-up when compared to MPI, OpenMP and sequential implementations, respectively. Compared to state-of-the-art, our solution reaches up to 17 speed-up. This work presents an efficient method to map the Full Search algorithm for Motion Estimation (ME) onto General Purpose Graphic Processing Unit (GPGPU) architectures using Compute Unified Device Architecture (CUDA) programming model. Our method jointly exploits the massive parallelism available in current GPGPU devices and the parallelism potential of Full Search algorithm. Our main goal is to evaluate the feasibility of video codecs implementation using GPGPUs and its advantages and drawbacks compared to other platforms. Therefore, for comparison reasons, three solutions were developed using distinct programming paradigms for distinct underlying hardware architectures: (i) a sequential solution for general-purpose processor (GPP); (ii) a parallel solution for multi-core GPP using OpenMP library; (iii) a distributed solution for cluster/grid machines using Message Passing Interface (MPI) library. The CUDA-based solution for GPGPUs achieves speed-up compatible to the indicated by the theoretical model for different search areas. Our GPGPU Full Search Motion Estimation provides 2×, 20× and 1664× speed-up when compared to MPI, OpenMP and sequential implementations, respectively. Compared to state-of-the-art, our solution reaches up to 17× speed-up. |
| Author | Maule, Marilena Zatt, Bruno Monteiro, Eduarda Bampi, Sergio Vizzotto, Bruno Diniz, Cláudio |
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| Cites_doi | 10.1007/978-1-4757-4474-3 10.1109/31.44348 10.1145/1730836.1730839 10.1007/s11265-006-4190-4 10.1109/ASAP.1995.522922 10.1109/ICME.2007.4284972 10.1002/wilm.10048 10.1109/ICME.2008.4607530 10.1109/ICALIP.2008.4590176 10.1023/A:1018785512609 |
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| References_xml | – reference: MPI: The Message Passing Interface (MPI) standard. http://www.mcs.anl.gov/research/projects/mpi/. Accessed 14 Dec 2011 – reference: Yang, S., Lin, T., Chien, S.: Real-time motion estimation for 1080p videos on graphics processing units with shared memory optimization. In: IEEE Workshop on Signal Processing Systems, 2009, SiPS 2009, pp. 297–302, 7–9 Oct (2009) – reference: Thrust: Thrust-Code at the speed of light. http://code.google.com/p/thrust/wiki/QuickStartGuide. Accessed 14 Dec 2011 – reference: Lin, C., Leou, J.: An adaptative fast full search motion estimation algorithm for H.264. In: Proceedings of the [S.l.]: IEEE, ISCAS 2005-IEEE International Symposium Circuits and Systems, pp. 1493–1496 (2005) – reference: Nvidia: NVIDIA Corporation. http://www.nvidia.com. Accessed 14 Dec (2011) – reference: BhaskaranV.KonstantinidesK.Image and Video Compression Standards: Algorithms and Architectures19992BostonKluwer – reference: Nvidia Cuda: NVIDIA CUDA Programming Guide. http://developer.download.nvidia.com/compute/cuda/3_0/toolkit/docs/NVIDIA_CUDA_ProgrammingGuide.pdf (2011). Accessed 14 Dec 2011 – reference: Xiru Cluster: Xiru Cluster member of Grid’5000. http://gppd.inf.ufrgs.br/cms/gppd/?q=en/resources-list. Accessed Mar 2012 – reference: OpenMP: The OpenMP API specification for parallel programming. Available at http://openmp.org/wp/ – reference: YangK.-M.SunM.-T.WuL.A family of VLSI designs for the motion compensation block-matching algorithmIEEE Transactions on Circuits and Systems198936101317132510.1109/31.44348 – reference: ITU-T Recommendation H.264/AVC (03/10): Advanced Video Coding for Generic Audiovisual Services (2010) – reference: GPGPU: General purpose computation on graphics hardware. http://gpgpu.org. Accessed Mar 2012 – reference: Suhring, K.: JM H.264/AVC Reference Software version 14.2: http://iphome.hhi.de/suehring/tml/download/. Accessed 14 Dec 2011 – reference: ITU-T Recommendation H.261: Video Codec for Audiovisual Services at p×64 kbit/s, Version 1, ITU-T (1990) – reference: Cheng, R., Yang, E. Liu, T.: speeding up motion estimation algorithms on CUDA technology. In: Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010, pp. 93–96, 22–24 September (2010) – reference: GPU Direct: Nvidia GPU Direct. http://developer.nvidia.com/gpudirect. Accessed June 2012 – reference: Nvidia Fermi: NVIDIA’s next generation CUDATM compute architecture, Fermi. http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf (2009). Accessed 14 Dec 201 – reference: Baglietto, P., Maresca, M., Migliaro, A., Migliardi, M.: Parallel implementation of the full search block matching algorithm for motion estimation. In: International Conference on Application Specific Array Processors, pp. 182–192, July (1995) – reference: Kung, M.C., Au, O.C, Wong, P.H.W., Chun, L.H.: Block based parallel motion estimation using programmable graphics hardware. In: Proceedings of IEEE International Conference on Audio, Language and Image Processing (ICALIP), pp. 7–9, Shanghai, China (2008) – reference: Kuhn, P.: Algorithms, Complexity Analysis and VLSI Architectures for MPEG4 Motion Estimation. Kluwer, Boston, p. 239, ISBN:0-7923-8516-0 (1999) – reference: Colic, A., Kalva, H., Furht, B.: Exploring NVIDIA-CUDA for video coding. In: Proceedings of the First Annual ACM SIGMM Conference on Multimedia systems (MMSys ’10), pp. 13–22. ACM, New York, NY, USA (2010) – reference: x264 codec: http://www.videolan.org/developers/x264.html. Accessed 14 Dec 2011 – reference: Lin, Y.-C., Li, P.-L, Chang, C.-H., Wu, C.-L., Tsao, Y.-M., Chien, S.-Y.: Multi-pass algorithm of motion estimation in video encoding for generic GPU. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4451–4454 (2006) – reference: Chen, W.-N., Hang, H.-M.: H.264/AVC motion estimation implementation on compute unified device architecture (CUDA). In: IEEE International Conference on Multimedia and Expo (ICME), pp. 697–700 (2008) – reference: Grid’5000: http://www.grid5000.fr/. Accessed 14 Dec 2011 – reference: TanM.SiegelJ.M.SiegelH.J.Parallel Implementations of Block-Based Motion Vector Estimation for Video Compression on Four Parallel Processing SystemsInternational Journal of Parallel Programming199927319522510.1023/A:1018785512609 – reference: Lee, C.-Y., Lin, Y.-C., Wu, C.-L., Chang, C.-H., Tsao, Y.-M., Chien, S.-Y.: Multi-pass and frame parallel algorithms of motion estimation in H.264/AVC for Generic GPU. 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| Snippet | This work presents an efficient method to map the
Full Search
algorithm for Motion Estimation (ME) onto General Purpose Graphic Processing Unit (GPGPU)... This work presents an efficient method to map the Full Search algorithm for Motion Estimation (ME) onto General Purpose Graphic Processing Unit (GPGPU)... |
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| SubjectTerms | Algorithms Coding standards Computer architecture Computer Science Devices Distributed processing Libraries Mathematical models Motion simulation Parallel processing Platforms Processor Architectures Programming Quality standards Search algorithms Searching Software Engineering/Programming and Operating Systems Studies Theory of Computation |
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| Title | Parallelization of Full Search Motion Estimation Algorithm for Parallel and Distributed Platforms |
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