A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

• Published in: IEEE open journal of circuits and systems Vol. 2; pp. 241 - 252
• Main Authors: Smith, Jennifer Pearl, Bailey, J. I., Tuthill, John, Stefanazzi, Leandro, Cancelo, Gustavo, Treptow, Ken, Mazin, Benjamin A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: Adaptive computing systems with FPGA components; array signal processing; Digital signal processing; Field programmable gate arrays; filter bank theory and design; Filter banks; Finite impulse response filters; Hardware description languages; high-level synthesis; high-performance computing and communication systems; Microwave filters; Signal distortion; Source code; Superconducting filters; Superconducting microwave devices; ultra-wideband (UWB) communications
• ISSN: 2644-1225; 2644-1225
• DOI: 10.1109/OJCAS.2020.3041208

Many digital signal processing applications require a channelizer capable of moving sections of the incoming spectrum to baseband quickly and efficiently with minimal spectral leakage and signal distortion. We report the design and implementation of a 4 GHz, 4096-branch, 8-tap, 2/1 oversampled polyphase channelizer implemented on a Xilinx RFSoC. The open-source design consists of only IP cores created using Vivado HLS (C++) and IP cores available in Vivado HLx and System Generator versions 2019.1+. The channelizer was tested using a PYNQ overlay and Jupyter Notebook (Python) hosted on the RFSoC embedded CPU. The design uses 24% of the LUTs, 9% of the DSP48s, and 11% of the BRAMs on the ZCU111 RFSoC evaluation board and meets timing constraints at 512 MHz. The oversampled polyphase channelizer suppresses spectral image components below −60 dB. This design provides the first example of an oversampled polyphase channelizer running on a system on a chip architecture created without direct use of hardware description language. The presented approach leverages high-level design tools and includes source code which can be readily adapted by other researchers and development teams without the need for specialist knowledge in high-performance FPGA design.