A sub-milliwatt audio-processing platform for digital hearing aids

We present a novel audio-processing platform, FlexEngine, which is composed of a 24-bit applicationspecific instruction-set processor （ASIP） and five dedicated accelerators. Acceleration instructions, compact instructions and repeat instruction are added into the ASIP＇s instruction set to deal with...

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Bibliographic Details
Published inJournal of semiconductors Vol. 35; no. 7; pp. 160 - 164
Main Author 袁甲 陈黎明 于增辉 黑勇
Format Journal Article
LanguageEnglish
Published 01.07.2014
Subjects
Acceleration
Accelerators
Algorithms
ASIP
Clocks
Hearing aids
Platforms
Semiconductors
Sleep
低功耗
助听器
平台
应用程序
指令集
种用
音频处理
Online AccessGet full text
ISSN1674-4926
DOI10.1088/1674-4926/35/7/075008

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Summary:We present a novel audio-processing platform, FlexEngine, which is composed of a 24-bit applicationspecific instruction-set processor （ASIP） and five dedicated accelerators. Acceleration instructions, compact instructions and repeat instruction are added into the ASIP＇s instruction set to deal with some core tasks of hearing aid algorithms. The five configurable accelerators are used to execute several of the most common functions of hearing aids. Moreover, several low power strategies, such as clock gating, data isolation, memory partition, bypass mode, sleep mode, are also applied in this platform for power reduction. The proposed platform is implemented in CMOS 130 nm technology, and test results show that power consumption of FlexEngine is 0.863 mW with the clock frequency of 8 MHz at Vdd = 1.0 V.
Bibliography:Yuan Jia, Chen Liming, Yu Zenghui, Hei Yong（Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China）
application-specific instruction-set processor （ASIP）; accelerator; low power; hearing aids
11-5781/TN
We present a novel audio-processing platform, FlexEngine, which is composed of a 24-bit applicationspecific instruction-set processor （ASIP） and five dedicated accelerators. Acceleration instructions, compact instructions and repeat instruction are added into the ASIP＇s instruction set to deal with some core tasks of hearing aid algorithms. The five configurable accelerators are used to execute several of the most common functions of hearing aids. Moreover, several low power strategies, such as clock gating, data isolation, memory partition, bypass mode, sleep mode, are also applied in this platform for power reduction. The proposed platform is implemented in CMOS 130 nm technology, and test results show that power consumption of FlexEngine is 0.863 mW with the clock frequency of 8 MHz at Vdd = 1.0 V.
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ISSN:1674-4926
DOI:10.1088/1674-4926/35/7/075008