LDBR: Low-deflection bufferless router for cost-sensitive network-on-chip design

• Published in: Microprocessors and microsystems Vol. 38; no. 7; pp. 669 - 680
• Main Authors: Li, Yuhai, Mei, Kuizhi, Liu, Yuehu, Zheng, Nanning, Xu, Yi
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.10.2014
• Subjects: Bufferless router; Buffers; Cost-sensitive; Deflection; Deflection routing; Low-deflection; Microprocessors; Network on chip; Networks; Packet transmission; Power consumption; Routers; Workload; Low-deflection; Bufferless router; Cost-sensitive; Network on chip; Deflection routing
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2014.07.007

[Display omitted] •Three deflection behavior models are constructed to analyze the causes of deflections in the conventional bufferless networks.•A novel bufferless router (LDBR) is presented for reducing the packet deflections.•A deflection routing based on turn model is presented for LDBR to reduce the packet deflections during transmission.•Experimental results show that LDBR is more energy-efficiency than other bufferless networks. In network-on-chip (NoC) designs, the bufferless router is more energy-efficient than the conventional router with buffers. However, in the bufferless network, deflections cause great performance loss. In this paper, three deflection models are firstly constructed for analyzing the causes of deflections. Then, we propose a low-deflection bufferless router (LDBR), in which a multi-channel network interface and a novel deflection routing based on turn model are designed for reducing the deflections during packet transmissions. Finally, LDBR is evaluated against the latest bufferless routers using synthetic and real-world traffic patterns. The experimental results exhibit that the deflection rate of LDBR network is reduced by 41% compared to other bufferless networks, and LDBR also shows superiority in cost and power consumption across all workloads.