丁丽华, 董. 邱. 张. 王. 王. (2015). Multi-bit upset aware hybrid error-correction for cache in embedded processors. Journal of semiconductors, 36(11), 48-52. https://doi.org/10.1088/1674-4926/36/11/114006
Chicago Style (17th ed.) Citation丁丽华, 董佳琪 邱柯妮 张伟功 王晶 王珍珍. "Multi-bit Upset Aware Hybrid Error-correction for Cache in Embedded Processors." Journal of Semiconductors 36, no. 11 (2015): 48-52. https://doi.org/10.1088/1674-4926/36/11/114006.
MLA (9th ed.) Citation丁丽华, 董佳琪 邱柯妮 张伟功 王晶 王珍珍. "Multi-bit Upset Aware Hybrid Error-correction for Cache in Embedded Processors." Journal of Semiconductors, vol. 36, no. 11, 2015, pp. 48-52, https://doi.org/10.1088/1674-4926/36/11/114006.
Warning: These citations may not always be 100% accurate.