Test Scheduling and Test Time Minimization of System-on-Chip using Modified BAT Algorithm

• Published in: IEEE access Vol. 10; p. 1
• Main Authors: Chandrasekaran, Gokul, Kumar, Neelam Sanjeev, Karthikeyan, P R, Vanchinathan, K, Priyadarshi, Neeraj, Twala, Bhekisipho
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.01.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; BAT Algorithm; Benchmark testing; Benchmarks; Circuits; Convergence; Evolutionary algorithms; Genetic algorithms; Global optimization; Heuristic algorithms; Heuristic methods; Loudness; Modified BAT Algorithm; Optimization; Scheduling; Semiconductors; System on chip; Test Scheduling; Test Time; Testing time
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2022.3224924

System-on-Chip (SoC) is a structure in which semiconductor components are integrated into a single die. As a result, testing time should be reduced to achieve a low cost for each chip. Effective test scheduling can reduce the SoC testing time, which is more challenging due to its complexity. In this paper, the modified BAT algorithm-based test scheduling is proposed. Testing is carried out on the SoC ITC'02 benchmark circuits. The Modified Bat method is a recently heuristic algorithm that performs global optimization by imitating bat echolocation. Compared to other state-of-the-art algorithms, the Modified BAT Optimization method reduces testing time on SoCs. This paper improves the algorithm's exploration process by adjusting the equation for bat loudness (A 0 ) and pulse emission rate (r). The modified BAT algorithm converges to the optimal solution faster. It has been used in 14 international standard test functions. The test results indicate that the modified BAT algorithm has a fast convergence speed, which minimizes the testing time compared to other evolutionary algorithms on the ITC'02 SoC benchmark circuits.