Effect of Topographical and Layout Factors on Gate CD Modeling for MOS Transistor Area - Izawa, M.; Kurihara, M.; Tanaka, J.; Kawai, K.; Yoshifuku, R.; Maruyama, T.; Fujiwara, N. (IEEE transactions on semiconductor manufacturing, 2009)
Keywords: Applied sciences; Compact disks; Design. Technologies. Operation analysis. Testing; Electrodes; Electronics; Etching; Exact sciences and technology; Gate electrode; Gates (circuits); Integrated circuit modeling; Integrated circuits; Integrated circuits by function (including memories and processors); Lithography; Mathematical models; Microelectronic fabrication (materials and surfaces technology); MOS devices; MOSFETs; plasma etching; Process control; Production; Random access memory; Semiconductor device modeling; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; shallow trench isolation; SRAM; SRAM chips; Static random access memory; Transistors; Static random access memory; Critical size; Trench technology; Process control; Random access memory; Polycrystal; MOS structure; Modeling; SRAM; Mean square error; Insulation technology; MOS devices; shallow trench isolation; ULSI circuit; Microelectronic fabrication; Reactive ion etching; Gate electrode; Plasma etching; Integrated circuit; MOS transistor; Root mean square value; Gates