Design and evaluation of a high throughput robust router for network-on-chip

Network-on-chip (NoC) systems have been proposed to achieve high-performance computing where multiple processors are integrated into one chip. As the number of cores increases and the chips are scaled in the deep submicron technology, the NoC systems become subject to physical manufacture defects an...

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Bibliographic Details
Published inIET computers & digital techniques Vol. 6; no. 3; pp. 173 - 179
Main Authors Alhussien, A., Wang, C., Bagherzadeh, N.
Format Journal Article
LanguageEnglish
Published Stevenage Institution of Engineering and Technology 01.05.2012
John Wiley & Sons, Inc
Subjects
Algorithms
Applied sciences
Channels
Chips
Design engineering
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Failure
Fault tolerance
Faults
Hardware
Input-output equipment
Integrated circuits
Integrated circuits by function (including memories and processors)
Routers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Testing, measurement, noise and reliability
Performance evaluation
Interconnection network
Supercomputing
Processor
Adaptive algorithm
Network architecture
Router
System on a chip
Failures
Deadlock
Fault tolerance
Integrated circuit
Robustness
Miniaturization
Fault tolerant system
Defect detection
Online AccessGet full text
ISSN1751-8601
1751-861X
DOI10.1049/iet-cdt.2011.0082

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Summary:Network-on-chip (NoC) systems have been proposed to achieve high-performance computing where multiple processors are integrated into one chip. As the number of cores increases and the chips are scaled in the deep submicron technology, the NoC systems become subject to physical manufacture defects and running-time vulnerability, which result in faults. The faults affect the performance and functionality of the NoC systems and result in communication malfunctions. In this study, a fault tolerant router design with an adaptive routing algorithm that tolerates faults in the network links and the router components is proposed. The approach does not require the use of virtual channels and assures deadlock freedom. Furthermore, the experimental results show that the proposed architecture can tolerate multiple failures and prove robustness and fault tolerance with negligible impact on the performance.
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ISSN:1751-8601
1751-861X
DOI:10.1049/iet-cdt.2011.0082